COTEST - New Techniques for Supporting Testability in Co-design Environments

This document describes the process we followed for assessing the feasibility and effectiveness of high-level test vector generation. An experimental analysis of the available high-level fault models is first reported, whose purpose is to identify a reference fault model that could be fruitfully used for evaluating testability of circuits by reasoning on their behavior, only. A prototypical high-level fault simulation tool is also described, whose purpose is to support the fault models analysis. Finally, a test generation algorithm is presented that generates high quality test vectors by exploiting the selected fault model and the described high-level fault simulator.